The semiconductor industry currently uses different types of semiconductor-based imagers, such as charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays, among others.
Because of the inherent limitations and expense of CCD technology, CMOS imagers have been increasingly used as low cost imaging devices. A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photodiode, a photogate or a photoconductor overlying a doped region of a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes a charge transfer section formed on the substrate adjacent the photodiode, photogate or photoconductor having a charge sensing node, typically a floating diffusion node, connected to the gate of a source follower output transistor. The imager may include at least one transistor for transferring charge from the charge accumulation region of the substrate to the floating diffusion node and also has a transistor for resetting the diffusion node to a predetermined charge level prior to charge transfer.
In a conventional CMOS imager, the active elements of a pixel cell typically perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. The charge at the floating diffusion node is converted to a pixel output voltage by the source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate.
CMOS imaging circuits of the type discussed above are generally known and discussed in, for example, Nixon et al., “256.times.256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046–2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452–453 (1994), the disclosures of which are incorporated by reference herein.
A schematic top view of a semiconductor wafer fragment of one exemplary CMOS sensor pixel four-transistor (4T) cell 10 is illustrated in FIG. 1. As it will be described below, the CMOS sensor pixel cell 10 includes a photo-generated charge accumulating area 21 in an underlying portion of the substrate. This area 21 is formed as a pinned photodiode 11, shown in FIG. 2, formed as part of a p-n-p structure within a substrate 20. The pinned photodiode is termed “pinned” because the potential in the photodiode is pinned to a constant value when the photodiode is fully depleted. It should be understood, however, that the CMOS sensor pixel cell 10 may include a photogate, photoconductor or other image to charge converting device, in lieu of a pinned photodiode, as the initial accumulating area 21 for photo-generated charge.
The CMOS image sensor 10 of FIG. 1 has a transfer gate 30 for transferring photoelectric charges generated in the charge accumulating region 21 to a floating diffusion region (sensing node) 25. The floating diffusion region 25 is further connected to a gate 50 of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having gate 60 for selectively gating the output signal to terminal 32. A reset transistor having gate 40 resets the floating diffusion region 25 to a specified charge level before each charge transfer from the charge accumulating region 21.
As noted, the charge accumulating region 21 may be formed as a pinned p-n-p photodiode 11 which has a p-type layer 24, an n-type region 26 and the p-type substrate 20. The pinned photodiode 11 includes two p-type regions 20, 24 and the n-type photodiode region 26 which is fully depleted at a pinning voltage. Impurity doped source/drain regions 22 (FIG. 1), preferably having n-type conductivity, are provided on either side of the transistor gates 40, 50, 60. The floating diffusion region 25 adjacent the transfer gate 30 is also preferable n-type.
FIG. 2 also illustrates a portion of trench isolation regions 15 formed adjacent the charge accumulating region 21. The trench isolation regions 15 are typically formed using a conventional STI process or by using a Local Oxidation of Silicon (LOCOS) process and serve to isolate pixels one from another. A translucent or transparent insulating layer 55 formed over the CMOS image sensor 10 is also illustrated in FIG. 2. Conventional processing methods are used to form, for example, contacts 32 (FIG. 1) in the insulating layer 55 to provide an electrical connection to the source/drain regions 22, the floating diffusion region 25, and other wiring to connect to gates and other connections in the CMOS image sensor 10.
PNP buried photodiodes, such as the pinned photodiode 11 of FIG. 2, are becoming increasingly popular for high efficiency image sensors, particularly for image sensors operating at smaller wavelengths of the visible spectrum, for example, at the blue wavelength. The pinned buried photodiode presents an advantage to a conventional CMOS imager in that it increases the efficiency of charge transfer, improves color response for blue light and decreases dark current (generation of thermally-created electrons that raise potential without any illumination), as described in detail in U.S. Pat. No. 5,181,093 and U.S. Pat. No. 6,297,070, for example.
CMOS imagers with pinned buried photodiodes have a drawback, however, in that the charge is not completely transferred from the photodiode charge collection region 26 to the floating diffusion node 25 due to the formation of various potential barriers at the transfer gate 30. One potential barrier is formed when charge depletes to the pinned (or maximum) potential, at which point the electrostatic potential at the buried charge collection region 26 is higher than the potential at the end of the transfer gate channel adjacent to the buried photodiode. When this occurs, the pinned buried photodiode potential is high enough for some of the electrons to stay back in the photodiode charge collection region 26 rather than to move into the transfer gate 30 and then onto the floating diffusion node 25.
Another potential barrier occurs between the transfer gate 30 and the floating diffusion node 25. After some electrons have been transferred to the floating diffusion node 25, the electrostatic potential of the floating diffusion decreases. This causes a lower potential level at the floating diffusion node end of the transfer gate, such that some of the electrons stay back in the transfer gate channel rather than moving into the floating diffusion node 25. The closing of the potential difference between the floating diffusion node 25 and the channel region under the transfer gate 30 causes backspilling of electrons from the floating diffusion node 25 to the transfer gate channel. This charge stored in the transfer gate channel will be spilled equally into the floating diffusion and the photodiode when the transfer gate is being turned off. However, if channel impurity gradient is present, this charge will be preferably directed into the floating diffusion node when the transfer gate is turned off.
Accordingly, an improved charge transfer between the buried photodiode and the transfer gate, and a subsequent charge transfer between the transfer gate and the floating diffusion node are desirable. An improved charge transfer would improve voltage swing on the floating diffusion made and confer a lower voltage operation. A device that is less likely to form potential barriers would also be more easily manufactured because it would be less sensitive to process variations. By suppressing potential barrier formation in the transfer gate region, backspilling of electrons from the floating diffusion node to the transfer gate channel could be reduced.
A method of fabricating an active pixel photosensor exhibiting these improvements is also needed.